Dandy_15

在网上查了半天的资料，还是没解决的方案，
看下面国外的论坛：http://www.edaboard.com/ftopic186601.html
WHEN I TRY TO create netlist in Capture CIS the flowing masseg appear,

#170 Warning [ALG0051] Pin "VSS" is renamed to "VSS#K5" after substituting illegal characters in Package G24V-3_7N , U0D1A: DSP - G24, Pg 17,20 - DSP - AFE IO (0.50, 0.90).

- the pin type = Power
- Pin name = VSS
- Connected to Net = GND_SIGNAL

i try to rename the pin to GND_SIGNAL but masseg still appears.
Hi

Check your ECR matrix, it will take off the warning/error message. You have to be very cautious while setting that.

The warning is to indicate that your "VSS" (Power) is getting short to "GND_SIGNAL". Also modify it to "AGND/DGND/GND".

The above two method should solve your problem.

Centiago

再看一下OrCAD官方论坛:http://www.chronology.com/forums/ShowPost.aspx?PostID=12807

illegal characters in schematic symbol???
  

All:

When generating the netlist, the following Warings occur:

#92 Warning [ALG0051] Pin "GND" is renamed to "GND#9" after substituting illegal characters in Package LT1765EFE
#99 Warning [ALG0051] Pin "Vss" is renamed to "VSS#34" after substituting illegal characters in Package IDT71016S ,
#79 Warning [ALG0051] Pin "VCC" is renamed to "VCC#1" after substituting illegal characters in Package H8S2168AA
#89 Warning [ALG0051] Pin "VIN" is renamed to "VIN#3" after substituting illegal characters in Package LT1765EFE

I very puzzled, and it seems that, GND, VSS, VCC, VIN are all illegal pin name in schmatic symbol, so tool rename them. Which names are illegal when creating schamtic symbl? I dont see any docs.
Maybe this problem is caused by same name in one schematic symbol, but I have set these pins with same name to "POWER" property. Previously, it is allowed same name if the pin property is power.

Thanks
Peter

You didn't say which netlister you were using but by the error msgs it looks like Allegro. You may have to consult the Allegro documentation to see if it objects to duplicate pin names. As an alternative, check the netlist itself -perhaps these pins are still connected to correct nets by pin number with pin name as a reference only ?

Ron O.

Dandy_15

最后看了一下Candence的Help文件，是这么说：
Pin Bubbles
Use the BUBBLE and BUBBLE_GROUP properties for tracking and checking signal states and circuit behavior. The pins need to be bubbled correctly

while they are being designed in Design Entry HDL. Symbols that are built correctly should not cause any problems and should successfully

complete the design integrity checks within Design Entry HDL. These properties also provide for much more readable designs when looked at

logically.
Cadence libraries include the DeMorgan equivalent parts as alternate symbol versions. When placing parts, the correct symbol should be used to

establish signal states and to provide design integrity. You can use the bubble command in Design Entry HDL to toggle the signal states on pins.


Pin Types
Designate the pin types and add pin loading information in Part Developer. This information gets stored in the chips.prt file and is crucial for

some Design Entry HDL integrity checks and layout analysis with SigNoise. Signal noise analysis uses the pin type and loading information to

accurately model the behavior of components.
The information can also be input manually into the chips.prt file by using a text editor. However, this requires you to be aware of the syntax

and file format.
Whenever appropriate the input pins should be placed on the left side of the symbol with outputs on the right.


Pin Naming
Pins should be designated with functional names. Each pin name must be unique to that symbol and must have a matching entry in the chips.prt

file. Typically, a pin name must be alphanumeric, but you can have numbers as pin names for scalar pins. The other characters that are supported

by Design Entry HDL as valid characters in pin names are as follows:
-
#
$
%
+
=
|
?
^
_
.
(
)

For pins that have ( or ) in their names, hlibftb reports errors if you run verification checks from within Part Developer. However, you can use

such pins in Design Entry HDL schematics by turning off the multi_format_vector option. Because of this reason, it is suggested that you do not

use ( or ) in pin names.

The following are not valid for pin names:
All extended character sets
/
;
!
<
>
:
\
"
,
*
When creating parts manually, place the SIG_NAME properties outside the symbol, next to the pin it is attached to. Text size is not too

important on these properties since they are not displayed on the schematic.
Follow low asserted pin names with an asterisk (*) (for example, OE*) or _N (for example OE_N). Do not differentiate low asserted pins with any

other nomenclature. All low asserted pins should appear as bubbles and not straight pin stubs.
设为Power可重名只是OrCAD的规定，那是OrCAD公司的规则，便Candence却不认同，Allegro是不准同名的，只要同名就有Warning,再看看Allegro的NETLIST，
'GND'
'@SR888.SCHEMATIC1(SCH_1):GND':
C_SIGNAL='@sr888.schematic1(sch_1):gnd';
NODE_NAME        U2 3
'@SR888.SCHEMATIC1(SCH_1):INS1860963@MY LIBRARY.MEGA88VS.NORMAL(CHIPS)':
'GND#3':;
NODE_NAME        U2 5
'@SR888.SCHEMATIC1(SCH_1):INS1860963@MY LIBRARY.MEGA88VS.NORMAL(CHIPS)':
'GND#5':;
这才明白，Allegro的NETLIST中pin name的信息，这样能重名吗？
再看看PADS的netlist:
*NET*
*SIGNAL* GND
U6.12 R14.2 R13.2 J6.10 J6.8 J6.6 U6.10 D10.2
D16.1 D15.1 U6.13 D17.1 J6.3 C8.2 C16.2 U2.5
C20.2 U2.3 C15.2 U6.5 C18.2 U5.3 U2.21 U4.3
C17.2 C25.2 C22.2 C6.1 C21.2 D8.2 J6.4 D18.1
U6.1 C19.2 C7.1 D4.1 D9.2 C24.2 D12.2 U6.11
D11.2 C23.2 J1.2 J1.4 MH13.1 MH12.1 MH6.1 C27.2
MH9.1 C29.2 MH5.1 J5.5 C30.2 C10.2 C31.2 C11.1
P2.5 J5.6 U7.7 C3.2 C26.2 C1.2 C2.2 U3.15
P2.10 C4.2 C28.2 J4.13 P1.5 C5.2 U1.2 C14.2
C9.2 J4.15 P1.10 P1.11 MH10.1 P2.11 MH8.1 U7.3
这样，没用pin name信息，当然可以重名了！

看来，没什么好想的，只能用#1,#2,#3来区分了，这样就知道是同一个地上的不同引脚，如果用1，2，3来分的话，不怎么好，DATA1,DATA2,DATA3，它也是用1，2，3来分的，名子也都是data，但不是同一网络。